1. Field of the Invention
This invention relates generally to the field of integrated circuit design and, more particularly, to the design of protection circuitry for providing protection against damaging effects of Electrostatic Discharge (ESD).
2. Description of the Related Art
Integrated circuits (ICs) are typically manufactured with external connections—most commonly pins—for coupling to external devices, systems, signals and/or power supply voltages. More recently, IC design and manufacturing has been trending towards an increase in the density of internal components, most commonly transistors and device interconnects, with a concurrent decrease in the power supply voltage levels used in operating the ICs. As IC devices increase in density and operating supply voltage levels decrease, the IC devices may become more sensitive to the effects of electrostatic discharge (ESD).
ESD many times originates from build up of static charge near the IC or on a human handling the IC, leading to extremely high voltages developed near the IC, and typically results in an electrical discharge of very high current for a short duration. Therefore, ESD poses a serious problem for semiconductor devices as it can potentially lead to malfunction and/or the destruction of an entire IC. In addition, the physical dimensions of circuit elements in many ICs, for example in microprocessors, have seen a decrease with each new generation of manufacturing process. Although smaller dimensions lead to an increase in IC operating speeds, they also have an adverse impact by increasing the sensitivity of circuit elements, such as field effect transistors (FETs), to high electric fields. One technique employed in overcoming this increased sensitivity has been to reduce the operating voltage of an IC. However, as supply voltages are scaled down (from 5.0 volts, to 3.3 volts, to 2.5, to 1.8 volts, for example), there is typically a need to maintain backward compatibility with the higher voltage requirements of older ICs.
In order to maintain compatibility with previous generations of semiconductor products and devices, it has been necessary to provide ICs with interface circuits that are interoperable with older generation ICs requiring higher supply voltages. One result of this has been the practice of designing ICs having a core operated using a first power supply voltage, and Input/Output (I/O) circuitry, typically around the physical periphery of the IC, operated using a higher power supply voltage. Since ESD events often occur across the silicon circuits attached to the package terminals, or pins, of an IC, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits. Often the design of ESD protection circuits has to satisfy high performance requirements. For example, one of the primary industry standards for measuring ESD robustness (MIL-STD-883C method 3015.7 Notice 8 (1989), and the subsequent Human Body Model (HBM) standard No. 5.1 (1993) from the EOS/ESD Association) requires ESD zapping for what can be a large number of pin and power supply combinations.
Generally formulated, protection against effects of ESD requires sensing either a predetermined voltage level, or the fast rate of voltage change resulting from an ESD pulse that might affect an integrated circuit component or an entire chip. The pins that require the ESD protection must generally be tolerant to voltages above the highest voltage tolerance of the typical FETs used in the fabrication process. Trigger circuits that may be used to turn on a clamp in response to any incoming ESD pulse would therefore have to be high voltage tolerant. In the past, ESD protection circuits have had difficulty meeting these stringent requirements while maintaining adequate noise immunity and without increasing the required silicon area.
In general, various techniques for improving ESD performance, including the use of semiconductor controlled rectifiers (SCRs), snapback devices, and rail clamps, have been devised, published and/or patented.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.